Recently, a recording/reproducing apparatus adopting a digital mode has been created for recording and/or reproducing digital information. Specifically, the apparatus converts video and audio signals into digital signals, and the digital signals are recorded on a magnetic recording medium via source encoding and channel encoding processes. Then, the digital signal may be reproduced from the recording medium via channel decoding and source decoding processes.
FIG. 1 shows a signal processing system in a digital videocassette recorder which comprises a recording portion and a reproducing portion. The recording portion contains first and second analog-to-digital (A/D) converters 110 and 120, a video data encoder 130, an error-correction encoder 140, a recording encoder 150, a recording amplifier 160, and a recording magnetic head HD1. The reproducing portion includes a playback magnetic head HD2, a playback amplifier 210, a data detector 220, an error-correction decoder 230, a video data decoder 240, and first and second digital-to-analog (D/A) converters 250 and 260.
In the recording portion, the first A/D converter 110 converts an analog video signal into a digital video signal, and the second converter 120 converts an analog audio signal into a digital audio signal. Then, the digital video signal is compressed in accordance with a high-efficiency code by the video data encoder 130, and the encoder 130 outputs corresponding compressed video data. Afterwards, the error-correction encoder 140 synthesizes the compressed video from the encoder 130 and the digital audio data from the A/D converter 120 to produce synthesized data. Then, the encoder 140 adds parity data to the synthesized data using an error correction code such as a Reed Solomon (RS) code to generate error-correction coded data.
The recording encoder 150 inputs the error-correction coded data and encodes such data to produce a compensated code. Then, the recording amplifier 160 amplifies the compensated code, and the amplified signal is recorded on a magnetic tape T via the recording magnetic head HD1.
The detailed configuration of the recording encoder 150 is shown in FIG. 2. In particular, the encoder 150 comprises a channel modulator 151, a precoder 152, and a recording compensation circuit 153. The channel modulator 151 inputs the error-correction coded data from the encoder 140, encodes such data using an 8-to-14 or 24-to-25 modulation scheme, and outputs corresponding channel modulated data. The precoder 152 converts the channel modulated data into a non-return-to-zero inversion (NRZI) code.
The recording compensation circuit 153 inputs the NRZI code, compensates for the deterioration of the recording characteristics associated with such code, and outputs a corresponding compensated code to the recording amplifier 160. The circuit 153 may comprise a recording equalizer (not shown) which equalizes the NRZI code in order to compensate for the deterioration, or alternatively, the recording equalizer may be provided separately from the compensation circuit 153.
Referring back to the reproducing portion of the apparatus shown in FIG. 1, a signal is reproduced from the magnetic tape T via the playback magnetic had HD2, and the reproduced signal is amplified by the playback amplifier 210 to produce an amplified signal. Afterwards, the data detector 220 detects the video and audio data contained in the amplified signal and outputs related channel decoded data. Then, the error-correction decoder 230 corrects any errors contained in the channel decoded data and outputs corresponding error corrected video data and error corrected audio data. The video data decoder 240 decodes the error corrected video data to produce decoded video data, and the decoded video data is converted into an analog video signal via the first D/A converter 250. On the other hand, the error corrected audio data is converted into an audio signal via the second D/A converter 260.
The internal structure of the data detector 220 is illustrated in FIG. 3. In particular, the detector 220 contains an automatic gain control (AGC) amplifier 221, a low pass filter 222, an A/D converter 223, an equalizer 224, a timing detector 225, a Viterbi decoding circuit 226, and a channel demodulator 227.
The AGC amplifier 221 inputs the amplified signal from the playback amplifier 210 and outputs an amplitude adjusted signal. The low-pass filter 222 removes any high-frequency noise contained in the amplitude adjusted signal and outputs a corresponding filtered signal. Then, the A/D converter 223 converts the filtered signal into digital data, and the equalizer 224 compensates for any distortion in the waveform and level of the digital data and outputs a corresponding equalized signal. The timing detector 225 detects the predetermined frequency and timing of the equalized signal via a phase-locked loop (PLL) circuit (not shown). Then, the detector 225 outputs a sampling clock to the A/D converter 223 and a driving clock (not shown) for other circuits of the reproducing portion. The Viterbi decoding circuit 226 Viterbi-decodes the equalized signal to produce Viterbi decoded data, and the channel demodulator 227 demodulates such data in accordance with the modulation scheme mentioned above to generate the channel demodulated data. Subsequently, the channel demodulated data is output to the error-correction decoder 230 shown in FIG. 1.
In order to increase the recording density of a signal without significantly changing the characteristics of conventional recording/reproducing systems, various technological advances have been utilized. For example, technologies relating to partial response maximum likelihood responses, including a Viterbi decoding process, have been advanced, and many circuits implementing such technologies have been introduced.
An example of a circuit which implements a Viterbi decoding process using an NRZI code having two states S.sub.-1 and S.sub.1 is shown in FIG. 4A. Specifically, the circuit contains a precoder 152, a magnetic recording/reproducing channel 200, an adder 201, and a Viterbi decoding circuit 226. (Please note that the precoder 152 and the Viterbi decoding circuit 226 are designated by the same reference numerals which designate the corresponding components in FIGS. 2 and 3).
The precoder 152 is referred to as a "1T precoder" or a "PR(1,-1) type system" and includes a delay 11 and a modulo-2 adder 12. The delay 11 inputs the data (e.g., NRZI code data) b.sub.k-1 output from the adder 12 at time k-1 and delays such data b.sub.k-1 by one bit to produce delayed data. Then, the adder 12 receives input data a.sub.k and the delayed data at time k, performs an exclusive OR operation on such data, and outputs NRZI code data b.sub.k at time k.
The magnetic recording/reproducing channel 200 has a differential characteristic (1-D), inputs the data b.sub.k, and outputs corresponding channel data z.sub.k having no noise. The adder 201 is used to introduce Gaussian noise into the channel for mathematical modeling purposes. Specifically, the adder 201 inputs the channel data z.sub.k and a noise signal n.sub.k and adds such signals z.sub.k and n.sub.k to produce a channel output y.sub.k. In other words, the channel output y.sub.k can be represented by equation (1): EQU y.sub.k =z.sub.k +n.sub.k (if n.sub.k =0, y.sub.k =z.sub.k)(1)
Then, the Viterbi decoding circuit 226 inputs the channel output y.sub.k and decodes the output y.sub.k to generate decoded data c.sub.k.
As shown in FIG. 4A and described above, the input data a.sub.k is binary coded information having a value of -1 or 1 at a time k, and the code data b.sub.k is output from the precoder 152 at time k. Furthermore, the value D is a delay operator for a one bit delay to delay the code data b.sub.k by one bit. In addition, the value (1-D) represents the differential characteristic of the magnetic recording/reproducing channel 200, and the channel data z.sub.k is output from the channel 200 at time k and introduces no noise. The noise n.sub.k represents the Gaussian noise which is superposed on the channel data z.sub.k at time k, and the channel output y.sub.k represents the signal which is input to the Viterbi decoding circuit 220 at time k. Finally, the decoded data c.sub.k is the data output from the decoding circuit at time k.
FIG. 4B depicts a state diagram of the operation of the precoder 152. Specifically, the precoder has two states S.sub.-1 (S=-1) and S.sub.1 (S=1) and the arrows in the figure represent potential transitions from one state to another state or back to the same state. In addition, the designations "X"/Y relating to each of the arrows represent signals which are input to and output from the system. In particular, the value X corresponds to the input data a.sub.k received by the precoder 152, and the value Y represents the channel data z.sub.k output from the magnetic recording/reproducing channel 200.
The relationship between the data a.sub.k input to the decoder 152 and the decoded data c.sub.k output from the Viterbi decoding circuit 226 is summarized in FIG. 5A. Also, FIG. 5B schematically shows the channel output y.sub.k supplied to the Viterbi decoder 226 when no noise n.sub.k is superposed upon the output y.sub.k, and FIG. 5C is a trellis diagram showing the state transition of the channel output y.sub.k.
In the normal operation of the apparatus illustrated in FIGS. 1-3, some noise is contained in the equalized signal output from the equalizer 224 and input to the Viterbi decoding circuit 226 (FIG. 3). This noise primarily results from granular particles adhered to the tape T, the impedance of the magnetic head HD2, the initial bias resistance of the playback amplifier 210, etc. Accordingly, since the reproduced signal passes through the head HD2, amplifier 210, equalizer 224, etc., the range of the equalized signal and the superposed noise is varied when the signal is input to the Viterbi decoding circuit 226.
As shown in FIG. 6A, the actual waveform of the equalized signal is an analog waveform in which the actual data and the superposed noise cannot be completely separated from one another and distinctly identified. Accordingly, the Viterbi decoding circuit 226 quantizes a positive direction amplitude of the normalized inputs (+1, 0, -1) as one of two values "H" and "L" via an H.sub.n detecting comparator (not shown) Specifically, the H.sub.n detecting comparator outputs positive peak data H.sub.n having the value "H" when the input signal is above the threshold "+1" and outputs positive peak data H.sub.n having the value "L" when the input signal is below the threshold "+1".
Similarly, the Viterbi decoding circuit 226 quantizes a negative direction amplitude of the normalized inputs (+1, 0, -1) as one of two values "H" and "L" via an L.sub.n detecting comparator (not shown). In particular, the L.sub.n detecting comparator outputs negative peak data L.sub.n having the value "H" when the input signal is below the threshold "-1" and outputs negative peak data L.sub.n having the value "L" when the input signal is above the threshold "+1".
Moreover, as mentioned above, the magnetic recording/reproducing channel 200 has a differential characteristic 1-D and the precoder 152 corresponds to a partial response type PR(1,-1) system. As a result, only positive peak data H.sub.n having a value "L" ("0") or negative peak data L.sub.n having a value "H" ("-1") is output after previous positive peak data H.sub.n having a value "H" ("+1") if no noise is present. In other words, positive peak data H.sub.n having a value of "+1" is never output after previous positive peak data H.sub.n having a value "+1" has been output. Similarly, only negative peak data L.sub.n having a value "L" ("0") or positive peak data H.sub.n having a value "H" ("+1") is output after previous negative peak data L.sub.n having a value "H" ("-1"). Consequently, negative peak data L.sub.n having a value "-1" is not output after previous negative peak data L.sub.n having a value "-1" has been output. FIG. 6B depicts a trellis diagram of the binary states S=1 and S=-1 during the operation of the Viterbi decoding circuit 226 when it receives the equalized signal shown in FIG. 6A.
On the other hand, as shown in FIG. 7A, when noise n.sub.k is superposed on the channel output y.sub.k that is input to the Viterbi decoding circuit 226, the principle described above may not be satisfied. In particular, the figure shows that the channel output (i.e., detection data) y.sub.k contains an error due to noise because the value "+1" is detected at the time k=5 after the value "+1" has been detected at the time k=3. Accordingly, since the precoder 152 is a partial response type PR(1, -1) system, the channel output y.sub.k is deemed to be corrupted by noise when a value "+1" is output after a value "+1" or if a value "-1" is output after the value "-1" (irrespective of the number of "0s" therebetween).
In order to properly determine the correct channel output y.sub.k, the Viterbi decoding process uses an index for determining the correct value of the detected data based on which path of the trellis diagram has the highest probability of being correct. In particular, the metrics for each path are calculated, a surviving path is determined based on such calculations, and information relating to the surviving path is stored in a memory. Thus, when new input data a.sub.k is input, the information relating to the final surviving path is read from memory and used to decode the data a.sub.k. As a result, the Viterbi decoding circuit 226 requires various devices such as an A/D converter, a microprocessor, an adder, etc.
However, if the states of the decoding circuit 226 are binary, a peak value of the signal in the positive direction ("positive peak value") and a peak value of the signal in the negative direction ("negative peak value") can replace the role of the values of the metrics of the trellis diagram. Thus, the circuit is preferably designed such that it can detect the positive peak value of the signal and maintain the level of such value as a new threshold value to detect subsequent positive peak values. Moreover, the circuit is preferably designed such that the threshold value for detecting the negative peak values is constantly updated. In other words, the new threshold for detecting the negative peak value should always be lower than the threshold for detecting the positive peak value by a predetermined value A.
In addition, the negative peak value is detected and maintained as the new threshold value for determining the next negative peak value. Specifically, the detected value is used as the new threshold value for detecting the value "-1" of the channel output y.sub.k and is simultaneously used to correct the threshold at which the value "+1" is detected by setting such threshold to be higher than the threshold for detecting the value "-1" by the quantity A. As a result, the system is prepared to detect the next positive peak value or the next negative peak value of the channel output y.sub.k.
If the circuit implements the above design, an error contained in the output y.sub.k can be detected and corrected. As shown in FIG. 7B, when consecutive "1"s or consecutive "0"s are detected, the leading one of the two data is deemed to be corrupted by noise. Thus, the state of the data is inverted.
The theory and research for interlocking the positive peak value and the negative peak value such that the difference between them is equals a predetermined offset (i.e. the value A) is described in an article entitled "Signal processing method PRML, achieving large capacity memory device of the next generation" in Japanese Nikkei Electronics, No. 599, pp. 72-97, January, 1994.
Referring to FIG. 8, the structure of a conventional Viterbi decoding circuit will be described. Such circuit is described in the following articles: "Optimal Reception for Binary Partial Response Channels" by M. J. Ferguson in Bell Syst. Tech. J., 51(2), pp. 493-505, February, 1972, and "Viterbi Detection of Class IV Partial Response on a Magnetic Recording Channel" by R. W. Wood and D. A. Petersen in IEEE Trans. Comm., Vol. Com-34, No. 5, pp. 454-461, May, 1986.
In FIG. 8, input data y.sub.k is quantized in an A/D converter (not shown) and has a value of -2, 0, or +2. Then, the data y.sub.k is supplied to an adder 232 and a sample-hold device 231, and the device 231 updates or maintains the value of the input data y.sub.k depending on a signal output from an exclusive OR gate 235. Specifically, when the state of the input data y.sub.k changes, the data output from the device 231 is updated. However, when the state of the data y.sub.k does not change, the sample-hold device 231 maintains the value of the data y.sub.k.
As shown in the trellis diagram illustrated in FIG. 7B, the original input data y.sub.k of the NRZI code are decoded to have the value "+1(H)" when the state S changes and are decoded to have the value "-1(L)" when the state S does not change. Preferably, the decoded result is written in the RAM 243 as "-1(L)" as a default when the state S does not change and is written as "+1(H)" when the state S changes.
When the state of the input data y.sub.k changes, the exclusive OR gate 235 outputs a "1", and the output of an exclusive OR gate 236 is written to a point address of the RAM 243 via a switch 239. Also, when the output of the exclusive OR gate 235 is "0", a value of "-1(L)" (e.g. GND) is written in an address of the RAM 243 via the switch 239. Accordingly, all of the decoded data c.sub.k are stored in the RAM 243.
In order to generate the point address, the counter 240 repetitively counts from zero to an upper limit. The upper limit is determined based on the word length of the decoded data word. For example, if the data is decoded by a unit of eight bits, the counter 240 repetitively counts from zero to seven. The point register 241 inputs the address counted by the counter 240 and the output of the exclusive OR gate 235 and outputs the point address such that the output of the exclusive OR gate 235 is transferred only when the states are changed.
On the other hand, as each new divergent point on the trellis diagram is established, one of the two potential paths is terminated. In other words, the establishment of each divergent point generates a new ambiguous bit and also settles some proceeding ambiguity. Accordingly, if the path diverges at a time P, a final surviving path from the previous time p is determined at the next divergent point. Thus, the change of the state S at the time p is known and the value "+1(H)" or "-1(L)" of the decoded data c.sub.k can be accurately written in the address p of the RAM 243 in response to the change of the state S.
However, when Viterbi decoding is performed on the basis of trellis diagrams, computing the value of the metric at each divergent point via a microprocessor and storing the result of such computation in memory is necessary. Thus, in the conventional Viterbi decoding circuit illustrated in FIG. 8, an A/D converter (not shown), a microprocessor (not shown), the RAM 243, and the address counter 240 are required. Thus, when the Viterbi decoding circuit is made into an integrated circuit (IC), the chip size and the cost of the IC are relatively large due to the addition of the components above. For example, sixty four comparators should be installed in a 6-bit flush type A/D converter which is used in a conventional Viterbi decoding circuit.